QoS Analysis for UCIe-based Cross-die Communication using Network Calculus

Chen YANG, Yuming JIANG, Zhonghai LU

RESCUE: Runtime Setup Resilience for TDM-Based Circuit-Switched NoCs

Yizhe Xiong, Zhonghai Lu

Long-Term Health Prediction for Power Diodes Using Non-Uniform Kalman Filter

Chao Guo, Zhonghai Lu

Digital-Twin-Assisted Hybrid Learning for Endurance Fatigue Prediction of HfZrOx Ferroelectric Diodes

Hongji Pei, Chao Guo, Zhonghai Lu

AsLDPC: Improving Decoding Performance With Absorbing Set Characteristic Aware Low-Density Parity-Check Code.

Lanlan Cui, Fei Wu 0005, Xiaojian Liu, Meng Zhang 0014, Zhonghai Lu, Miao Li, Changsheng Xie 0001

Bit Transition Reduction by Data Transmission Ordering in NoC-based DNN Accelerator.

Yizhi Chen, Jingwei Li, Wenyao Zhu, Zhonghai Lu

High-Precision Low-Latency Method and Architecture for Computing Binary and Decimal Logarithms.

Hui Chen 0015, Lianghua Quan, Weiqiang Liu 0001, Zhonghai Lu

NoCDAS: A Cycle-Accurate NoC-Based Deep Neural Network Accelerator Simulator.

Wenyao Zhu, Yizhi Chen, Zhonghai Lu

Integrating Self-Organizing Map and Graph Neural Networks to Detect Anomalies in Time-Series Data

Peng Su, Hengzhen Yuan, Zhonghai Lu, Dejiu Chen

Applying Reinforcement Learning to Protect Deep Neural Networks from Soft Errors

Peng Su, Yuhang Li, Zhonghai Lu, Dejiu Chen

Self-Adaptive RUL Prediction of Power Electronic Devices with Package Failure

Chao Guo, Zhonghai Lu

Health Condition Prediction of Power Diodes Using Particle Filter

Chao Guo, Zhonghai Lu

Amputee Gait Phase Recognition Using Multiple GMM-HMM.

Wenyao Zhu, Zhenbang Liu, Yizhi Chen, De-Jiu Chen, Zhonghai Lu

Automatic Generation and Optimization Framework of NoC-Based Neural Network Accelerator Through Reinforcement Learning.

Yongqi Xue, Jinlun Ji, Xinming Yu, Shize Zhou, Siyue Li, Xinyi Li, Tong Cheng, Shiping Li, Kai Chen 0034, Zhonghai Lu, Li Li 0003, Yuxiang Fu

Communication Synchronization-Aware Arbitration Policy in NoC-Based DNN Accelerators.

Wenjie Fan 0004, Siyue Li, Lingxiao Zhu, Zhonghai Lu, Li Li 0003, Yuxiang Fu

Heterogeneous Reconfigurable Accelerator for Homomorphic Evaluation on Encrypted Data.

Wenqing Song, Sirui Shen, Congwei Xu, Yilin Wang, Xinyu Wang 0027, Yuxiang Fu, Li Li 0003, Zhonghai Lu

Impact of Image Sensor Input Faults on Pruned Neural Networks for Object Detection.

Yizhi Chen, Wenyao Zhu, De-Jiu Chen, Omar Mohammed, Parthib Khound, Zhonghai Lu

MCLB: Dynamic Load Balancing and Implications on GPU Memory Controllers.

Vahid Geraeinejad, Kun-Chih Jimmy Chen, Zhonghai Lu, Masoumeh Ebrahimi

Pooling On-the-Go for NoC-Based Convolutional Neural Network Accelerator.

Wenyao Zhu, Yizhi Chen, Zhonghai Lu

Travel Time-Based Task Mapping for NoC-Based DNN Accelerator.

Yizhi Chen, Wenyao Zhu, Zhonghai Lu

Health Condition Estimation for Discrete Power Electronic Devices under Package Failure

Zhonghai Lu, Alexander Otto

RUL Estimation for Power Electronic Devices Using RNNs

Congrui Cai, Zhonghai Lu

Computational Network-on-Chip as Convolution Engine

Zhonghai Lu, Mingrui Liu

Activation in Network for NoC-Based Deep Neural Network Accelerator

Wenyao Zhu, Yizhi Chen, Zhonghai Lu

A NoC-Based Spatial DNN Inference Accelerator With Memory-Friendly Dataflow.

Lingxiao Zhu, Wenjie Fan 0004, Chenyang Dai, Shize Zhou, Yongqi Xue, Zhonghai Lu, Li Li 0003, Yuxiang Fu

Age Feature Enhanced Neural Network for RUL Estimation of Power Electronic Devices.

Zhonghai Lu, Rui Shi, Chao Guo, Mingrui Liu

Combining Self-Organizing Map with Reinforcement Learning for Multivariate Time Series Anomaly Detection.

Peng Su, Zhonghai Lu, De-Jiu Chen

FlexZNS: Building High-Performance ZNS SSDs with Size-Flexible and Parity-Protected Zones.

Yu Wang 0168, You Zhou 0009, Zhonghai Lu, Xiaoyi Zhang, Kun Wang 0029, Feng Zhu 0024, Shu Li, Changsheng Xie 0001, Fei Wu 0005

Health warning based on 3R ECG Sample's combined features and LSTM.

Qingshan Liu, Cuiyun Gao, Yang Zhao, Songqun Huang, Yuqing Zhang, Xiaoyu Dong, Zhonghai Lu

Holistic and Opportunistic Scheduling of Background I/Os in Flash-Based SSDs.

Yu Wang 0168, You Zhou 0009, Fei Wu 0005, Yu Zhong, Jian Zhou 0004, Zhonghai Lu, Shu Li, Zhengyong Wang, Changsheng Xie 0001

PiN: Processing in Network-on-Chip.

Zhonghai Lu

Remaining useful lifetime estimation for discrete power electronic devices using physics-informed neural network

Zhonghai Lu, Chao Guo, Mingrui Liu, Rui Shi

RUL Estimation for Package Failure of Power Electronic Devices Using Integral Mean of Precursor Signal

Zhonghai Lu, Chao Guo, Pol Ghesquiere, Kai Kriegel, Gerhard Mitic

Damage-Based Lifetime Modeling for Power Electronic Devices

Chao Guo, Zhonghai Lu

RUL Estimation for Power Electronic Devices Based on LESIT Equation

Zhonghai Lu, Rui Shi, Alexander Otto, Jan Albrecht

A Hierarchical Parallel Discrete Gaussian Sampler for Lattice-Based Cryptography.

Sirui Shen, Wenqing Song, Xinyu Wang 0027, Xinyu Shao, Yuxiang Fu, Zhonghai Lu, Li Li 0003

A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash.

Lanlan Cui, Xiaojian Liu, Fei Wu 0005, Zhonghai Lu, Changsheng Xie 0001

Accelerating Non-Negative Matrix Factorization on Embedded FPGA with Hybrid Logarithmic Dot-Product Approximation.

Yizhi Chen, Yarib Nevarez, Zhonghai Lu, Alberto García-Ortiz

Base-2 Softmax Function: Suitability for Training and Efficient Hardware Implementation.

Yuan Zhang, Yonggang Zhang 0005, Lele Peng, Lianghua Quan, Shubin Zheng, Zhonghai Lu, Hui Chen 0015

Enabling Energy-Efficient Inference for Self-Attention Mechanisms in Neural Networks.

Qinyu Chen, Congyi Sun, Zhonghai Lu, Chang Gao 0002

Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture.

Boqian Wang, Zhonghai Lu

Huicore: A Generalized Hardware Accelerator for Complicated Functions.

Hui Chen 0015, Zongguang Yu, Jin Xu, Lin Jiang, Zhonghai Lu, Yuxiang Fu, Li Li 0003

Inference Time Reduction of Deep Neural Networks on Embedded Devices: A Case Study.

Isma-Ilou Sadou, Seyed Morteza Nabavinejad, Zhonghai Lu, Masoumeh Ebrahimi

Online Image Sensor Fault Detection for Autonomous Vehicles.

Yizhi Chen, Wenyao Zhu, De-Jiu Chen, Zhonghai Lu

Redundancy Reduction for Sensor Deployment in Prosthetic Socket: A Case Study.

Wenyao Zhu, Yizhi Chen, Siu-Teing Ko, Zhonghai Lu

Wearable pressure sensing for lower limb amputees.

Zhonghai Lu, Wenyao Zhu, Yizhi Chen, Josephine Charnley, Valter Dejke, Andrii Pomazanskyi, Siu-Teing Ko, Begum Zeybek, Pouyan Mehryar, Zulfiqur Ali, Michalis Karamousadakis, De-Jiu Chen

A Configurable Hardware Architecture for Runtime Application of Network Calculus.

Xiao Hu, Zhonghai Lu

A General Methodology and Architecture for Arbitrary Complex Number Nth Root Computation.

Hui Chen 0015, Ruiqi Wu, Zhonghai Lu, Yuxiang Fu, Li Li 0003, Zongguang Yu

DEPS: Exploiting a Dynamic Error Prechecking Scheme to Improve the Read Performance of SSD.

Weihua Liu, Fei Wu 0005, Meng Zhang 0014, Chengmo Yang, Zhonghai Lu, Jiguang Wan 0001, Changsheng Xie 0001

Dynamic and Traffic-Aware Medium Access Control Mechanisms for Wireless NoC Architectures.

Qian Gao, Wenqing Song, Zhonghai Lu, Li Li 0003, Yuxiang Fu

Evaluation of Time Series Clustering on Embedded Sensor Platform.

Wenyao Zhu, Zhonghai Lu

Guest Editorial: IEEE TC Special Issue On Communications for Many-core Processors and Accelerators.

Zhonghai Lu

Low-Complexity High-Precision Method and Architecture for Computing the Logarithm of Complex Numbers.

Hui Chen 0015, Zongguang Yu, Yonggang Zhang 0005, Zhonghai Lu, Yuxiang Fu, Li Li 0003

Modeling of Threshold Voltage Distribution in 3D NAND Flash Memory.

Weihua Liu, Fei Wu 0005, Jian Zhou 0004, Meng Zhang 0014, Chengmo Yang, Zhonghai Lu, Yu Wang 0168, Changsheng Xie 0001

Optimal Sprinting Pattern in Thermal Constrained CMPs.

Jian Wang 0024, Zhe Chen, Shize Guo, Yubai Li, Zhonghai Lu

Symmetric-Mapping LUT-Based Method and Architecture for Computing XY-Like Functions.

Hui Chen 0015, Heping Yang, Wenqing Song, Zhonghai Lu, Yuxiang Fu, Li Li 0003, Zongguang Yu

The Impact of Faults on DNNs: A Case Study.

Elaheh Malekzadeh, Nezam Rohbani, Zhonghai Lu, Masoumeh Ebrahimi

A CORDIC-Based Architecture with Adjustable Precision and Flexible Scalability to Implement Sigmoid and Tanh Functions.

Hui Chen 0015, Lin Jiang, Yuanyong Luo, Zhonghai Lu, Yuxiang Fu, Li Li 0003, Zongguang Yu

A Novel Approximation Methodology and Its Efficient VLSI Implementation for the Sigmoid Function.

Zidi Qin, Yuou Qiu, Huaqing Sun, Zhonghai Lu, Zhongfeng Wang 0001, Qinghong Shen, Hongbing Pan

A Universal Approximation Method and Optimized Hardware Architectures for Arithmetic Functions Based on Stochastic Computing.

Zidi Qin, Yuou Qiu, Muhan Zheng, Hongxi Dong, Zhonghai Lu, Zhongfeng Wang 0001, Hongbing Pan

Advance Virtual Channel Reservation.

Boqian Wang, Zhonghai Lu

An Efficient Accelerator for Multiple Convolutions From the Sparsity Perspective.

Qinyu Chen, Yan Huang, Rui Sun, Wenqing Song, Zhonghai Lu, Yuxiang Fu, Li Li 0003

BlockHammer: Improving Flash Reliability by Exploiting Process Variation Aware Proactive Failure Prediction.

Ruixiang Ma, Fei Wu 0005, Zhonghai Lu, Wenmin Zhong, Qiulin Wu, Jiguang Wan 0001, Changsheng Xie 0001

Efficient Support of AXI4 Transaction Ordering Requirements in Many-Core Architecture.

Boqian Wang, Zhonghai Lu

Hyperbolic CORDIC-Based Architecture for Computing Logarithm and Its Implementation.

Hui Chen 0015, Kaifeng Cheng, Zhonghai Lu, Yuxiang Fu, Li Li 0003

Pursuing Extreme Power Efficiency With PPCC Guided NoC DVFS.

Yuan Yao 0009, Zhonghai Lu

Securing IoT Space via Hardware Trojan Detection.

Shize Guo, Jian Wang 0024, Zhe Chen, Yubai Li, Zhonghai Lu

Supporting QoS in AXI4 Based Communication Architecture.

Boqian Wang, Zhonghai Lu

An Adaptive Resource Provisioning Scheme for Industrial SDN Networks.

Matthias Becker 0004, Zhonghai Lu, De-Jiu Chen

ANN Based Admission Control for On-Chip Networks.

Boqian Wang, Zhonghai Lu, Shenggang Chen

Bit-Flipping Schemes Upon MLC Flash: Investigation, Implementation, and Evaluation.

Wenhui Zhang 0005, Qiang Cao 0001, Zhonghai Lu

Characterizing the Reliability and Threshold Voltage Shifting of 3D Charge Trap NAND Flash.

Weihua Liu, Fei Wu 0005, Meng Zhang 0014, Yifei Wang, Zhonghai Lu, Xiangfeng Lu, Changsheng Xie 0001

Competence Networks in the Era of CPS - Lessons Learnt in the ICES Cross-Disciplinary and Multi-domain Center.

Martin Törngren, Fredrik Asplund, Tor Ericson, Catrin Granbom, Erik Herzog, Zhonghai Lu, Mats Magnusson, Maria Månsson, Stefan Norrwing, Johanna Olsson, Johnny Öberg

Congestion-Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs.

Yuxiang Fu, Qinyu Chen, Guoqiang He, Kai Chen 0034, Zhonghai Lu, Chuan Zhang 0001, Li Li 0003

Hardware Acceleration of Multilayer Perceptron Based on Inter-Layer Optimization.

Shenggang Chen, Zhonghai Lu

NR-MPA: Non-Recovery Compression Based Multi-Path Packet-Connected-Circuit Architecture of Convolution Neural Networks Accelerator.

Gaoming Du, Zhenwen Yang, Zhenmin Li, Duoli Zhang, Yongsheng Yin, Zhonghai Lu

RBER-Aware Lifetime Prediction Scheme for 3D-TLC NAND Flash Memory.

Ruixiang Ma, Fei Wu 0005, Meng Zhang 0014, Zhonghai Lu, Jiguang Wan 0001, Changsheng Xie 0001

SCORE: A Novel Scheme to Efficiently Cache Overlong ECCs in NAND Flash Memory.

You Zhou 0009, Fei Wu 0005, Zhonghai Lu, Xubin He, Ping Huang 0001, Changsheng Xie 0001

Security-Aware Task Mapping Reducing Thermal Side Channel Leakage in CMPs.

Shize Guo, Jian Wang 0024, Zhe Chen, Zhonghai Lu, Jinhong Guo, Lian Yang

Smilodon: An Efficient Accelerator for Low Bit-Width CNNs with Task Partitioning.

Qinyu Chen, Yuxiang Fu, Kaifeng Cheng, Wenqing Song, Zhonghai Lu, Li Li 0003, Chuan Zhang 0001

SSS: Self-aware System-on-chip Using a Static-dynamic Hybrid Method.

Gaoming Du, Guanyu Liu, Zhenmin Li, Yifan Cao, Duoli Zhang, Yiming Ouyang, Minglun Gao, Zhonghai Lu

Toward FPGA Security in IoT: A New Detection Technique for Hardware Trojans.

Zhe Chen, Shize Guo, Jian Wang 0024, Yubai Li, Zhonghai Lu

A New Parallel CODEC Technique for CDMA NoCs.

Jian Wang 0024, Shize Guo, Zhe Chen, Yubai Li, Zhonghai Lu

A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition.

Xiaowen Chen, Yuanwu Lei, Zhonghai Lu, Shuming Chen

Cache Access Fairness in 3D Mesh-Based NUCA.

Zicong Wang, Xiaowen Chen, Zhonghai Lu, Yang Guo 0003

Characterizing 3D Charge Trap NAND Flash: Observations, Analyses and Applications.

Fei Wu 0005, Yue Zhu, Qin Xiong, Zhonghai Lu, You Zhou 0009, Weizhen Kong, Changsheng Xie 0001

Characterizing 3D Floating Gate NAND Flash: Observations, Analyses, and Implications.

Qin Xiong, Fei Wu 0005, Zhonghai Lu, Yue Zhu, You Zhou 0009, Yibing Chu, Changsheng Xie 0001, Ping Huang 0001

Composable Worst-Case Delay Bound Analysis Using Network Calculus.

Yanchen Long, Zhonghai Lu, Haibin Shen

Exploiting Minipage-Level Mapping to Improve Write Efficiency of NAND Flash.

Hao Lv, You Zhou 0009, Fei Wu 0005, Weijun Xiao, Xubin He, Zhonghai Lu, Changsheng Xie 0001

iNPG: Accelerating Critical Section Access with In-network Packet Generation for NoC Based Many-Cores.

Yuan Yao 0009, Zhonghai Lu

Program error rate-based wear leveling for NAND flash memory.

Xin Shi, Fei Wu 0005, Shunzhuo Wang, Changsheng Xie 0001, Zhonghai Lu

RoB-Router : A Reorder Buffer Enabled Low Latency Network-on-Chip Router.

Cunlu Li, Dezun Dong, Zhonghai Lu, Xiangke Liao

Thread Voting DVFS for Manycore NoCs.

Zhonghai Lu, Yuan Yao 0009

Towards QoS-Aware Service-Oriented Communication in E/E Automotive Architectures.

Matthias Becker 0004, Zhonghai Lu, De-Jiu Chen

Twelfth IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018, Torino, Italy, October 4-5, 2018

WARD: Wear Aware RAID Design Within SSDs.

Shunzhuo Wang, Fei Wu 0005, Zhonghai Lu, Jiaona Zhou, Changsheng Xie 0001

xMAS-Based QoS Analysis Methodology.

Zhonghai Lu, Xueqian Zhao

A Methodological Framework for Model-Based Self-management of Services and Components in Dependable Cyber-Physical Systems.

De-Jiu Chen, Zhonghai Lu

A Model-Based Approach to Dynamic Self-assessment for Automated Performance and Safety Awareness of Cyber-Physical Systems.

De-Jiu Chen, Zhonghai Lu

A Tool for xMAS-Based Modeling and Analysis of Communication Fabrics in Simulink.

Xueqian Zhao, Zhonghai Lu

ALARM: A Location-Aware Redistribution Method to Improve 3D FG NAND Flash Reliability.

Yue Zhu, Fei Wu 0005, Qin Xiong, Zhonghai Lu, Changsheng Xie 0001

Characterizing 3D Floating Gate NAND Flash.

Qin Xiong, Fei Wu 0005, Zhonghai Lu, Yue Zhu, You Zhou 0009, Yibing Chu, Changsheng Xie 0001, Ping Huang 0001

Dynamic Traffic Regulation in NoC-Based Systems.

Zhonghai Lu, Yuan Yao 0009

Extending Real-Time Analysis for Wormhole NoCs.

Qin Xiong, Fei Wu 0005, Zhonghai Lu, Changsheng Xie 0001

Lifetime adaptive ECC in NAND flash page management.

Shunzhuo Wang, Fei Wu 0005, Zhonghai Lu, You Zhou 0009, Qin Xiong, Meng Zhang 0014, Changsheng Xie 0001

Marginal Performance: Formalizing and Quantifying Power Over/Under Provisioning in NoC DVFS.

Zhonghai Lu, Yuan Yao 0009

Prediction based convolution neural network acceleration: work-in-progress.

Yuan Yao 0009, Zhonghai Lu

Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017, Seoul, Republic of Korea, October 19 - 20, 2017

Proceedings of the Fourth Workshop on Cryptography and Security in Computing Systems, CS2@HiPEAC 2017, Stockholm, Sweden, January 24, 2017

Quality-of-service-aware adaptation scheme for multi-core protocol processing architecture.

Mohammad Badawi, Zhonghai Lu, Ahmed Hemani

Round-trip DRAM Access Fairness in 3D NoC-based Many-core Systems.

Xiaowen Chen, Zhonghai Lu, Sheng Liu 0001, Shuming Chen

SSS: self-aware system-on-chip using static-dynamic hybrid method (work-in-progress).

Gaoming Du, Shibi Ma, Zhenmin Li, Zhonghai Lu, Yiming Ouyang, Minglun Gao

ACO-Based Thermal-Aware Thread-to-Core Mapping for Dark-Silicon-Constrained CMPs

Jian Wang, Zhe Chen, Jinhong Guo, Yubai Li, Zhonghai Lu

A 101.4 GOPS/W Reconfigurable and Scalable Control-Centric Embedded Processor for Domain-Specific Applications.

Yuxiang Huan, Ning Ma, Jia Mao, Stefan Blixt, Zhonghai Lu, Zhuo Zou, Li-Rong Zheng 0001

A New CDMA Encoding/Decoding Method for on-Chip Communication Network.

Jian Wang 0024, Zhonghai Lu, Yubai Li

Aggregate Flow-Based Performance Fairness in CMPs.

Zhonghai Lu, Yuan Yao 0009

Design and implementation of multi-mode routers for large-scale inter-core networks.

Ning Ma, Zhuo Zou, Zhonghai Lu, Li-Rong Zheng 0001

DVFS for NoCs in CMPs: A thread voting approach.

Yuan Yao 0009, Zhonghai Lu

Elastic Management and QoS Provisioning Scheme for Adaptable Multi-core Protocol Processing Architecture.

Mohammad Badawi, Zhonghai Lu, Ahmed Hemani

Memory-access aware DVFS for network-on-chip in CMPs.

Yuan Yao 0009, Zhonghai Lu

Multi-bit transient fault control for NoC links using 2D fault coding method.

Xiaowen Chen, Zhonghai Lu, Yuanwu Lei, Yaohua Wang, Shenggang Chen

OLITS: An Ohm's Law-like traffic splitting model based on congestion prediction.

Gaoming Du, Yanghao Ou, Xiangyang Li, Ping Song, Zhonghai Lu, Minglun Gao

Opportunistic Competition Overhead Reduction for Expediting Critical Section in NoC Based CMPs.

Yuan Yao 0009, Zhonghai Lu

Real-Time Analysis for Wormhole NoC: Revisited and Revised.

Qin Xiong, Zhonghai Lu, Fei Wu 0005, Changsheng Xie 0001

Service-Guaranteed Multi-port Packet Memory for Parallel Protocol Processing Architecture.

Mohammad Badawi, Zhonghai Lu, Ahmed Hemani

Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip.

Fahimeh Jafari, Axel Jantsch, Zhonghai Lu

A High-Level Thermal Model-Based Task Mapping for CMPs in Dark-Silicon Era

Jian Wang, Zhonghai Lu, Yubai Li, Yusheng Fu, Jinhong Guo

Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs.

Xiaowen Chen, Zhonghai Lu, Yang Li, Axel Jantsch, Xueqian Zhao, Shuming Chen, Yang Guo 0003, Zonglin Liu, Jianzhuang Lu, Jianghua Wan, Shuwei Sun, Shenggang Chen, Hu Chen

Backlog Bound Analysis for Virtual-Channel Routers.

Xueqian Zhao, Zhonghai Lu

Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips.

Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Yang Guo 0003, Shenggang Chen, Hu Chen, Man Liao

Exploring stacked main memory architecture for 3D GPGPUs.

Yuang Zhang, Li Li 0003, Axel Jantsch, Zhonghai Lu, Minglun Gao, Yuxiang Fu, Hongbing Pan

Heuristics-Aided Tightness Evaluation of Analytical Bounds in Networks-on-Chip.

Xueqian Zhao, Zhonghai Lu

Highway in TDM NoCs.

Shaoteng Liu, Zhonghai Lu, Axel Jantsch

Implementing MVC Decoding on Homogeneous NoCs: Circuit Switching or Wormhole Switching.

Ning Ma, Zhuo Zou, Zhonghai Lu, Li-Rong Zheng 0001

Least Upper Delay Bound for VBR Flows in Networks-on-Chip with Virtual Channels.

Fahimeh Jafari, Zhonghai Lu, Axel Jantsch

MultiCS: Circuit switched NoC with multiple sub-networks and sub-channels.

Shaoteng Liu, Axel Jantsch, Zhonghai Lu

Performance Analysis of Homogeneous On-Chip Large-Scale Parallel Computing Architectures for Data-Parallel Applications.

Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Yang Guo 0003, Shenggang Chen, Hu Chen

Performance analysis of on-chip bufferless router with multi-ejection ports.

Chaochao Feng, Zhuofan Liao, Zhonghai Lu, Axel Jantsch, Zhenyu Zhao

Validating Delay Bounds in Networks on Chip: Tightness and Pitfalls.

Alberto Saggio, Gaoming Du, Xueqian Zhao, Zhonghai Lu

A Fair and Maximal Allocator for Single-Cycle On-Chip Homogeneous Resource Allocation.

Shaoteng Liu, Axel Jantsch, Zhonghai Lu

A hierarchical reconfigurable micro-coded multi-core processor for IoT applications.

Ning Ma, Zhuo Zou, Zhonghai Lu, Li-Rong Zheng 0001, Stefan Blixt

A survey of memory architecture for 3D chip multi-processors.

Yuang Zhang, Li Li 0003, Zhonghai Lu, Axel Jantsch, Minglun Gao, Hongbing Pan, Feng Han 0008

An analytical model for worst-case reorder buffer size of multi-path minimal routing NoCs.

Gaoming Du, Miao Li, Zhonghai Lu, Minglun Gao, Chunhua Wang

Analysis and evaluation of per-flow delay bound for multiplexing models.

Yanchen Long, Zhonghai Lu, Xiaolang Yan

Cooperative communication for efficient and scalable all-to-all barrier synchronization on mesh-based many-core NoCs.

Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Yang Guo 0003, Hengzhu Liu

Customizable coarse-grained energy-efficient reconfigurable packet processing architecture.

Mohammad Badawi, Ahmed Hemani, Zhonghai Lu

Empowering study of delay bound tightness with simulated annealing.

Xueqian Zhao, Zhonghai Lu

Fuzzy flow regulation for Network-on-Chip based chip multiprocessors systems.

Yuan Yao 0009, Zhonghai Lu

Item-Level Indoor Localization With Passive UHF RFID Based on Tag Interaction Analysis.

Zhi Zhang, Zhonghai Lu, Vardan Saakian, Xing Qin, Qiang Chen 0014, Li-Rong Zheng 0001

Parallel probe based dynamic connection setup in TDM NoCs.

Shaoteng Liu, Axel Jantsch, Zhonghai Lu

Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips.

Yuang Zhang, Li Li 0003, Zhonghai Lu, Axel Jantsch, Yuxiang Fu, Minglun Gao

Towards stochastic delay bound analysis for Network-on-Chip.

Zhonghai Lu, Yuan Yao 0009, Yuming Jiang 0001

Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router.

Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang, Zuocheng Xing

An Analytical Latency Model for Networks-on-Chip.

Abbas Eslami Kiasari, Zhonghai Lu, Axel Jantsch

Analysis and Evaluation of Circuit Switched NoC and Packet Switched NoC.

Shaoteng Liu, Axel Jantsch, Zhonghai Lu

Code division multiple access/pulse position modulation ultra-wideband radio frequency identification for Internet of Things: concept and analysis.

Zhi Zhang, Zhonghai Lu, Qiang Chen 0014, Xiaolang Yan, Li-Rong Zheng 0001

Efficient distributed memory management in a multi-core H.264 decoder on FPGA.

Jiajie Zhang, Zheng Yu 0001, Zhiyi Yu, Kexin Zhang, Zhonghai Lu, Axel Jantsch

Mathematical formalisms for performance evaluation of networks-on-chip.

Abbas Eslami Kiasari, Axel Jantsch, Zhonghai Lu

Per-flow delay bound analysis based on a formalized microarchitectural model.

Xueqian Zhao, Zhonghai Lu

Reducing Virtual-to-Physical address translation overhead in Distributed Shared Memory based multi-core Network-on-Chips according to data property.

Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Shenggang Chen, Huitao Gu

Scalability Analysis of Memory Consistency Models in NoC-Based Distributed Shared Memory SoCs.

Abdul Naeem, Axel Jantsch, Zhonghai Lu

A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip.

Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang

A single-cycle output buffered router with layered switching for Networks-on-Chips.

Yancang Chen, Zhonghai Lu, Lunguo Xie, Jinwen Li, Minxuan Zhang

A Survey of FPGA Dynamic Reconfiguration Design Methodology and Applications.

Ming Liu 0011, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch

An Enhanced IOT Gateway in a Broadcast System.

Xianyang Jiang, Deshi Li, Shaobo Nie, Jing Luo, Zhonghai Lu

Analytical approaches for performance evaluation of networks-on-chip.

Abbas Eslami Kiasari, Axel Jantsch, Marco Bekooij, Alan Burns 0001, Zhonghai Lu

Architecture Support and Comparison of Three Memory Consistency Models in NoC Based Systems.

Abdul Naeem, Axel Jantsch, Zhonghai Lu

Design and Optimization of a CDMA-Based Multi-Reader Passive UHF RFID System for Dense Scenarios.

Zhi Zhang, Zhonghai Lu, Qiang Chen 0014, Xiaolang Yan

Dynamic Flow Regulation for IP Integration on Network-on-Chip.

Zhonghai Lu, Yi Wang

Modeling and Power Evaluation of On-Chip Router Components in Spintronics.

Pierre Schamberger, Zhonghai Lu, Xianyang Jiang, Meikang Qiu

Parallel probing: Dynamic and constant time setup procedure in circuit switching NoC.

Shaoteng Liu, Axel Jantsch, Zhonghai Lu

Performance Analysis of Flow-Based Traffic Splitting Strategy on Cluster-Mesh Sensor Networks.

Huimin She, Zhonghai Lu, Axel Jantsch, Dian Zhou, Li-Rong Zheng 0001

Scalability analysis of release and sequential consistency models in NoC based multicore systems.

Abdul Naeem, Axel Jantsch, Zhonghai Lu

Self-selection pseudo- circuit: a clever crossbar pre-allocation.

Wenmin Hu, Hengzhu Liu, Zhonghai Lu, Axel Jantsch, Guitao Fu

Support Efficient and Fault-Tolerant Multicast in Bufferless Network-on-Chip.

Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang, Xianju Yang

System-level evaluation of sensor networks deployment strategies: Coverage, lifetime and cost.

Huimin She, Zhonghai Lu, Axel Jantsch

Three-phase time-aware energy minimization with DVFS and unrolling for Chip Multiprocessors.

Meikang Qiu, Zhong Ming 0001, Jiayin Li, Shaobo Liu, Bin Wang 0002, Zhonghai Lu

TPSS: A Flexible Hardware Support for Unicast and Multicast on Network-on-Chip.

Wenmin Hu, Zhonghai Lu, Hengzhu Liu, Axel Jantsch

Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling.

Fahimeh Jafari, Axel Jantsch, Zhonghai Lu

Worst-case performance analysis of 2-D mesh NoCs using multi-path minimal routing.

Gaoming Du, Cunqiang Zhang, Zhonghai Lu, Alberto Saggio, Minglun Gao

A High-End Reconfigurable Computation Platform for Nuclear and Particle Physics Experiments.

Ming Liu 0011, Wolfgang Kuehn, S. Lange, Shuo Yang, J. Roskoss, Zhonghai Lu, Axel Jantsch, Qiang Wang, Hao Xu, Dapeng Jin

A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip.

Chaochao Feng, Minxuan Zhang, Jinwen Li, Jiang Jiang, Zhonghai Lu, Axel Jantsch

Cooperative communication based barrier synchronization in on-chip mesh architectures.

Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Hai Liu

Cross clock-domain TDM virtual circuits for networks on chips.

Zhonghai Lu

Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations.

Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Zhonghai Lu, Dimitrios Soudris, Axel Jantsch

Evaluation of deflection routing on various NoC topologies.

Chaochao Feng, Jinwen Li, Zhonghai Lu, Axel Jantsch, Minxuan Zhang

FPGA-Based Cherenkov Ring Recognition in Nuclear and Particle Physics Experiments.

Ming Liu 0011, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch

FPGA-Based Particle Recognition in the HADES Experiment.

Ming Liu 0011, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch

Hybrid Distributed Shared Memory Space in Multi-core Processors.

Xiaowen Chen, Shuming Chen, Zhonghai Lu, Axel Jantsch

Jamming-resilient multi-radio multi-channel multihop wireless network for smart grid.

Hai Su, Meikang Qiu, Huimin Chen, Zhonghai Lu, Xiao Qin 0001

Modeling and analysis of Rayleigh fading channels using stochastic network calculus.

Huimin She, Zhonghai Lu, Axel Jantsch, Dian Zhou, Li-Rong Zheng 0001

Network-on-Chip multicasting with low latency path setup.

Wenmin Hu, Zhonghai Lu, Axel Jantsch, Hengzhu Liu, Botao Zhang 0002, Dongpei Liu

Output process of variable bit-rate flows in on-chip networks based on aggregate scheduling.

Fahimeh Jafari, Axel Jantsch, Zhonghai Lu

Power-efficient tree-based multicast support for Networks-on-Chip.

Wenmin Hu, Zhonghai Lu, Axel Jantsch, Hengzhu Liu

Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systems.

Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jantsch

Realization and Scalability of Release and Protected Release Consistency Models in NoC Based Systems.

Abdul Naeem, Axel Jantsch, Xiaowen Chen, Zhonghai Lu

Stochastic coverage in event-driven sensor networks.

Huimin She, Zhonghai Lu, Axel Jantsch, Dian Zhou, Li-Rong Zheng 0001

System design of full HD MVC decoding on mesh-based multicore NoCs.

Ning Ma, Zhonghai Lu, Li-Rong Zheng 0001

Adaptively reconfigurable controller for the flash memory

Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch

Memory architecture and management in an NoC platform

Axel Jantsch, Xiaowen Chen, Abdul Naeem, Yuang Zhang, Sandro Penolazzi, Zhonghai Lu

A framework for designing congestion-aware deterministic routing.

Abbas Eslami Kiasari, Axel Jantsch, Zhonghai Lu

A Low Delay Multiple Reader Passive RFID System Using Orthogonal TH-PPM IR-UWB.

Zhi Zhang, Zhonghai Lu, Zhibo Pang, Xiaolang Yan, Qiang Chen 0014, Li-Rong Zheng 0001

A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip.

Chaochao Feng, Zhonghai Lu, Axel Jantsch, Jinwen Li, Minxuan Zhang

Analysis of Worst-Case Delay Bounds for On-Chip Packet-Switching Networks.

Yue Qian, Zhonghai Lu, Wenhua Dou

Buffer Optimization in Network-on-Chip Through Flow Regulation.

Fahimeh Jafari, Zhonghai Lu, Axel Jantsch, Mohammad Hossien Yaghmaee

COSMO: CO-Simulation with MATLAB and OMNeT++ for Indoor Wireless Networks.

Zhi Zhang, Zhonghai Lu, Qiang Chen 0014, Xiaolang Yan, Li-Rong Zheng 0001

FoN: Fault-on-Neighbor aware routing algorithm for Networks-on-Chip.

Chaochao Feng, Zhonghai Lu, Axel Jantsch, Jinwen Li, Minxuan Zhang

FPGA-based adaptive computing for correlated multi-stream processing.

Ming Liu 0011, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch

Handling shared variable synchronization in multi-core Network-on-Chips with distributed memory.

Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen

Inter-process Communication Using Pipes in FPGA-Based Adaptive Computing.

Ming Liu 0011, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch

Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach.

Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch, Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrjä, Fragkiskos Ieromnimon, Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, Philippe Martin 0005

Optimal regulation of traffic flows in networks-on-chip.

Fahimeh Jafari, Zhonghai Lu, Axel Jantsch, Mohammad Hossien Yaghmaee

QoS scheduling for NoCs: Strict Priority Queueing versus Weighted Round Robin.

Yue Qian, Zhonghai Lu, Qiang Dou

Reducing FPGA Reconfiguration Time Overhead using Virtual Configurations.

Ming Liu 0011, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch

Run-Time Partitioning of Hybrid Distributed Shared Memory on Multi-core Network-on-Chips.

Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen

Scalability of weak consistency in NoC based multicore architectures.

Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jantsch

Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller.

Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen

Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique.

Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Jianzhuang Lu, Hucheng Wu

System-level exploration of mesh-based NoC architectures for multimedia applications.

Ning Ma, Zhonghai Lu, Zhibo Pang, Li-Rong Zheng 0001

The MOSART Mapping Optimization for Multi-Core ARchiTectures.

Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch, Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrjä, Fragkiskos Ieromnimon, Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, Philippe Martin 0005

Third International Workshop on Network on Chip Architectures, NoCArc'10, Atlanta, GA, USA, December 4, 2010

Multi-FPGA Implementation of a Network-on-Chip Based Many-core Architecture with Fast Barrier Synchronization Mechanism

Xiaowen Chen, Shuming Chen, Zhonghai Lu, Axel Jantsch

Area and Performance Optimization of Barrier Synchronization on Multi-core Network-on-Chips

Xiaowen Chen, Shuming Chen, Zhonghai Lu, Axel Jantsch

3-D memory organization and performance analysis for multi-processor network-on-chip architecture.

Awet Yemane Weldezion, Zhonghai Lu, Roshan Weerasekera, Hannu Tenhunen

A flow regulator for On-Chip Communication.

Zhonghai Lu, Dimitris Brachos, Axel Jantsch

A Reconfigurable Design Framework for FPGA Adaptive Computing.

Ming Liu 0011, Zhonghai Lu, Wolfgang Kuehn, Shuo Yang, Axel Jantsch

Analysis of communication delay bounds for network on chips.

Yue Qian, Zhonghai Lu, Wenhua Dou

Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chip.

Yue Qian, Zhonghai Lu, Wenhua Dou

Analytical Evaluation of Retransmission Schemes in Wireless Sensor Networks.

Huimin She, Zhonghai Lu, Axel Jantsch, Dian Zhou, Li-Rong Zheng 0001

Analyzing Credit-Based Router-to-Router Flow Control for On-Chip Networks.

Yue Qian, Zhonghai Lu, Wenhua Dou, Qiang Dou

Applying network calculus for performance analysis of self-similar traffic in on-chip networks.

Yue Qian, Zhonghai Lu, Wenhua Dou

Exploration of Slot Allocation for On-Chip TDM Virtual Circuits.

Li Tong, Zhonghai Lu, Hua Zhang

Flow regulation for on-chip communication.

Zhonghai Lu, Mikael Millberg, Axel Jantsch, Alistair C. Bruce, Pieter van der Wolf, Tomas Henriksson

From 2D to 3D NoCs: A case study on worst-case communication performance.

Yue Qian, Zhonghai Lu, Wenhua Dou

Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh.

Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuwa, Roshan Weerasekera, Zhonghai Lu, Axel Jantsch, Dave Shippen

Run-time Partial Reconfiguration speed investigation and architectural design space exploration.

Ming Liu 0011, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch

Scalability of network-on-chip communication architecture for 3-D meshes.

Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Zhonghai Lu, Axel Jantsch, Roshan Weerasekera, Hannu Tenhunen

Scalability of relaxed consistency models in NoC based multicore architectures.

Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jantsch

Worst-Case Flit and Packet Delay Bounds in Wormhole Networks on Chip.

Yue Qian, Zhonghai Lu, Wenhua Dou

Resource Allocation for QoS On-Chip Communication

Axel Jantsch, Zhonghai Lu

Trends of terascale computing chips in the next ten years

Zhonghai Lu, Axel Jantsch

Speedup Analysis of Data-Parallel Applications on Multi-core NoCs

Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen

Trigger algorithm development on FPGA-based compute nodes

Ming Liu, Axel Jantsch, Dapeng Jin, Andreas Kopp, Wolfgang Kuehn, Johannes Lang, Lu Li, Soeren Lange, Zhen'an Liu, Zhonghai Lu, David Muenchow, Vladimir Pechenov, Johannes Roskoss, Stephano Spataro, Qiang Wang, Hao Xu

Hardware/software co-design of an ATCA-based computation platform for data acquisition and triggering

Qiang Wang, Axel Jantsch, Dapeng Jin, Andreas Kopp, Wolfgang Kuehn, Johannes Lang, Soeren Lange, Lu Li, Ming Liu, Zhen'an Liu, Zhonghai Lu, David Muenchow, Johannes Roskoss, Hao Xu

Applying Network Calculus for Worst-case Delay Bound Analysis in On-chip Networks

Yue Qian, Zhonghai Lu, Wenhua Dou

Towards Hierarchical Cluster based Cache Coherence for Large-Scale Network-on-Chip

Yuang Zhang, Zhonghai Lu, Axel Jantsch, Li Li, Minglun Gao

Comparative Analysis of Worst-Case Communication Delay Bounds for 2D and 3D NoCs

Yue Qian, Zhonghai Lu, Wenhua Dou

ATCA-based computation platform for data acquisition and triggering in particle physics experiments.

Ming Liu 0011, Johannes Lang, Shuo Yang, Tiago Perez, Wolfgang Kuehn, Hao Xu, Dapeng Jin, Qiang Wang, Lu Li, Zhen'An Liu, Zhonghai Lu, Axel Jantsch

Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip.

Zhonghai Lu, Lei Xia, Axel Jantsch

Dynamic TDM virtual circuit implementation for NoC.

Yu Wang 0002, Kai Zhou, Zhonghai Lu, Huazhong Yang

System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments.

Ming Liu 0011, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch

TDM Virtual-Circuit Configuration for Network-on-Chip.

Zhonghai Lu, Axel Jantsch

Analysis of Traffic Splitting Mechanisms for 2D Mesh Sensor Networks

Huimin She, Zhonghai Lu, Axel Jantsch, Li-Rong Zheng, Dian Zhou

Deterministic Worst-case Performance Analysis for Wireless Sensor Networks

Huimin She, Zhonghai Lu, Axel Jantsch, Li-Rong Zheng, Dian Zhou

Admitting and ejecting flits in wormhole-switched networks on chip.

Zhonghai Lu, Axel Jantsch

Design and Analysis of On-Chip Communication for Network-on-Chip Platforms.

Zhonghai Lu

Hardware/Software Co-design of a General-Purpose Computation Platform in Particle Physics.

Ming Liu 0011, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch, Shuo Yang, Tiago Perez, Zhen'An Liu

Layered Switching for Networks on Chip.

Zhonghai Lu, Ming Liu 0011, Axel Jantsch

Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip.

Zhonghai Lu, Axel Jantsch

Traffic Splitting with Network Calculus for Mesh Sensor Networks.

Huimin She, Zhonghai Lu, Axel Jantsch, Li-Rong Zheng 0001, Dian Zhou

Using Synchronizers for Refining Synchronous Communication onto Hardware/Software Architectures.

Zhonghai Lu, Jonas Sicking, Ingo Sander, Axel Jantsch

A Network-based System Architecture for Remote Medical Applications

Huimin She, Zhonghai Lu, Axel Jantsch, Li-Rong Zheng, Dian Zhou

Connection-oriented Multicasting in Wormhole-switched Networks on Chip.

Zhonghai Lu, Bei Yin, Axel Jantsch

Evaluation of on-chip networks using deflection routing.

Zhonghai Lu, Mingchen Zhong, Axel Jantsch

Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication.

Zhonghai Lu, Ingo Sander, Axel Jantsch

Refining synchronous communication onto network-on-chip best-effort services

Zhonghai Lu, Ingo Sander, Axel Jantsch

Feasibility analysis of messages for on-chip networks using wormhole routing.

Zhonghai Lu, Axel Jantsch, Ingo Sander

Refinement of Perfectly Synchronous Communication Model.

Zhonghai Lu, Ingo Sander, Axel Jantsch

Traffic Configuration for Evaluating Networks on Chips.

Zhonghai Lu, Axel Jantsch

NNSE: Nostrum network-on-chip simulation environment

Zhonghai Lu, Rikard Thid, Mikael Millberg, Erland Nilsson, Axel Jantsch

Flit admission in on-chip wormhole-switched networks with virtual channels.

Zhonghai Lu, Axel Jantsch

Flit ejection in on-chip wormhole-switched networks with virtual channels

Zhonghai Lu, Axel Jantsch

Development and Application of Design Transformations in ForSyDe.

Ingo Sander, Axel Jantsch, Zhonghai Lu

NoC Application Programming Interfaces.

Zhonghai Lu, Raimo Haukilahti

Network-on-Chip application programming interfaces: High level communication primitives and operating system services for power management

Zhonghai Lu, Raimo Haukilahti

A Case Study of Hardware and Software Synthesis in ForSyDe.

Ingo Sander, Axel Jantsch, Zhonghai Lu